1. Field of the Invention
The present invention relates to an analog-to-digital converter and, particularly, to an analog-to-digital converter including first and second preamplifiers that amplify a value of an analog input signal based on different reference voltages and comparators that convert an interpolation signal interpolating the outputs of the first and second preamplifiers into a digital value.
2. Description of Related Art
Recently, in the signal processing field, signal processing based on digital signals has become mainstream. Thus, if an externally input signal is a signal having an analog value (which is referred to hereinafter as an analog signal), the analog signal is converted to a digital signal and processed. One of circuits that perform such conversion processing is an analog-to-digital converter. The analog-to-digital converter includes a comparator that compares a value of an input analog signal with a value of a reference signal and converts the analog signal to a digital signal. The comparator, however, generally has an offset. Due to the offset, in the comparator, a threshold for inverting the logic level of an output signal is deviated from a voltage value of a reference voltage. In order to perform analog-to-digital conversion with high accuracy, it is necessary to reduce the deviation of the threshold. One approach to eliminate the threshold deviation is to reduce the threshold deviation of the comparator by calibration processing.
Examples of calibration processing are disclosed in U.S. Pat. No. 6,847,320 and Journal of Solid and State Circuits, Vol. 39, No. 12, December 2004, P2107-2115, “A 1.8-V 1.6-GSample/s 8-b Self-Calibrating Folding ADC With 7.26 ENOB at Nyquist Frequency”, Robert C. Taft et al. As an example of calibration processing, U.S. Pat. No. 6,847,320 is described hereinafter. FIG. 17 is a block diagram of an analog-to-digital converter 100 disclosed in U.S. Pat. No. 6,847,320. Referring to FIG. 17, in the analog-to-digital converter 100, an analog signal VIN is amplified by an amplifier 102 and an amplifier 104 and output to a node 156. On the other hand, the analog signal VIN is also amplified by an amplifier 106 and an amplifier 108 and output to a node 158. The amplifiers 102 and 106 amplify a voltage difference between a reference voltage generated by a reference voltage generator 110 and the analog signal VIN. Further, the amplifiers 104 and 108 have a single-end output structure. In the analog-to-digital converter 100, an interpolator 120 is placed between the node 156 and the node 158. The interpolator 120 generates an interpolation signal that interpolates a voltage of the node 156 and a voltage of the node 158.
The analog-to-digital converter 100 further includes a comparator CMPN0 that converts a voltage of the node 156 into a digital value, a comparator CMPN-10 that converts a voltage of the node 158 into a digital value, and comparators CMPN1 to CMPN2, and CMPN-11 that output digital signals based on the interpolation signal. The comparators CMPN0 to CMPN2, CMPN-10 and CMPN-11 are supplied with outputs of the amplifiers 104 and 108 and an output of the interpolator 120. Then, the comparators CMPN0 to CMPN2, CMPN-10 and CMPN-11 output digital values based on an input voltage and a preset threshold (a set value stored in each comparator).
At this time, in the analog-to-digital converter 100, an offset voltage of the amplifier 102 and the amplifier 104 is adjusted by a resistor Radj,N placed between the amplifier 102 and the amplifier 104 and a current Iadj,N output from a current source N. Further, an offset voltage of the amplifier 106 and the amplifier 108 is adjusted by a resistor Radj,N−1 placed between the amplifier 106 and the amplifier 108 and a current Iadj,N−1 output from a current source N−1.
The linearity of voltage values output to the nodes 156 and 158 is thereby improved. Thus, in the analog-to-digital converter 100, the offset voltage of the amplifiers 102, 104, 106, 108 are adjusted and the outputs of the amplifiers 104 and 108 are input to the comparators CMPN0 to CMPN2, CMPN-10 and CMPN-11, so that the linearity between the analog signal and the output digital signals is improved.